1. Field of the Invention
The present invention relates generally to clock signals in integrated circuits. Specifically, the present invention relates to reduction of clock skew in clock signals provided to multiple locations in the integrated circuit.
2. State of the Art
Digital integrated circuits typically include multiple logic elements, with the timing of operation of each logic element controlled by a clock signal. It is common for an integrated circuit chip to have one central clock generator, with the signal from the clock generator being distributed around the integrated circuit via clock-line interconnects. An important consideration in the design of synchronous digital integrated circuits, and in particular those using pipelined architecture, is variation in the arrival times of clock signals at the clock inputs of the various logic elements. See, K. Yip, “Clock tree distribution: balance is essential for a deep-submicron ASIC design to flourish,” IEEE Potentials, vol. 16, no. 2, pp. 11–14, April–May 1997. Variation in clock signal arrival time is referred to as clock skew.
Clock skew is primarily a function of two parameters: the loading presented by the logic being clocked and the RC delay of the clock line interconnect. Interconnect factors that affect the clock skew are the resistance, capacitance and inductance of the interconnection wires. Since the wires are not ideal conductors, different lengths of the wires carrying clock signals can result in different clock skews. Clock skew adds to cycle times, reducing the clock rate at which a chip can operate. Typically, skew should be 10 percent or less of a chip's clock cycle, meaning that for a 100 MHz clock, skew must be 1 nsec or less. High performance microprocessors may require skew to be 5 percent of the clock cycle, or 100 psec at a 500 MHz clock rate. See, K. M. Carrig et al., “Clock methodology for high-performance microprocessors,” Proc. Custom Integrated Circuits Conference, Santa Clara, Calif., May 5–8, pp. 119–122, 1997.
As noted above, it is relatively common to use a single, central clock generator to produce a signal that is distributed around the integrated circuit. A variety of techniques have been used in the prior art to provide clock connections that are symmetrical and all of the same length, in order to minimize clock skew at the various logic elements.
FIG. 1A illustrates an H-tree clock distribution, which is used primarily in custom layouts and has varying tree interconnect segment widths to balance skew throughout the chip.
FIG. 1B shows a clock grid clock distribution structure. The clock grid is the simplest clock distribution structure and has the advantage of being easy to design for low skew. However, it is area inefficient and power hungry because of the large amount of clock interconnect required. Nevertheless, some chip vendors are using this clock structure for microprocessors.
FIG. 1C depicts a balanced tree clock distribution structure. The balanced tree is the clock distribution structure most commonly used in high performance chips. See, J. L. Neves et al., “Automated synthesis of skew-based clock distribution networks,” VLSI Design, vol. 7, no. 1, pp. 31–57, 1998. In order to carry current to the branching segments, the clock line is widest at the root of the tree and becomes progressively narrower at each branch. As a result, the clock line capacitance increases exponentially with distance from the leaf cell (clocked element) in the direction of the root of the tree (clock input). Moreover, additional chip area is required to accommodate the extra clock line width in the regions closer to the root of the tree.
As shown in FIG. 1D, buffers may be added at the branching points of the balanced tree structure. Adding buffers at the branching points of the tree significantly lowers clock interconnect capacitance, because it reduces the clock line width required toward the root.
As noted above, two main factors that contribute to clock skew are loading mismatch at the clocked elements and mismatch in RC delay due to clock line segment width and length variations. The approaches discussed above and illustrated in FIGS. 1A–1D attempt to minimize clock skew caused by these factors. Most designers and clock tree parasitic extraction/evaluation tools available today deal only with RC parasitics. However, clock skew is also influenced by inductance effects, which become more prominent as clock edge times and interconnect resistances decrease, both of which are associated with shrinking chip technology and higher clock rates. For these reasons, minimization of skew due to inductance effects has become the biggest problem in the design of clock trees, and, similarly, has become a significant problem in the design of today's leading edge chips.
Designers have not commonly considered parasitic inductance, but this is starting to change as clock frequencies approach 1 GHz. Clock trees often have wide traces at their roots and may also have long segments, making the trees more susceptible to inductance problems than are other chip networks. Careful layout, including placing power and ground lines next to, above, or below clock trees to act as shields, can help reduce the possibility of clock problems caused by inductance.
Clock skew may also be influenced by process variations induced during chip fabrication.
Various techniques have been previously described for compensating for the different delays of individual clock distribution lines by changing the line characteristics or driver characteristics. Many new techniques have been considered for addressing clock skew problems. One technique involves the generation of clock signals with various delays by using digital inverters or amplifiers with various signal delays, and multitapped variable delay lines. See, K. Ishibashi et al., “Novel clock distribution system for CMOS VLSI,” Proc. IEEE Int. Conference on Computer Design: VLSI in Computers and Processors, October 3–6, Cambridge, Mass., pp. 289–292, 1993. Another technique involves the use of buffer amplifiers with different skews to compensate for the different line delays. See, T. Knight et al., “Method for skew-free distribution of digital signals using matched variable delay lines,” Symposium on VLSI Circuits, Kyoto, Japan, May 19–21, pp. 19–20, 1993; see also S. I. Liu et al., “Low-power clock-deskew buffer for high speed digital circuits,” IEEE J. Solid-State Circuits, Vol. 34, No. 4, pp. 554–558, 1999. Clock skew problems have also been addressed using feedback techniques to compensate for the effects of the variable line delays. See, H. Sutoh et al., “A Clock Distribution Technique with an Automatic Skew Compensation Circuit,” Inst. of Electronic, Information and Communication Engineers, Japan, Vol. E8 1-C, No. 2, pp. 277–283, 1998. Furthermore, optical clock distribution techniques are also used. See, A. V. Mule et al., “10 GHz Hybrid optical/electrical clock distribution network for gigascale integration,” Proceeding of the 1999 12th Annual Meeting IEEE Lasers and Electro-Optics Society, San Francisco, Calif., November 1999, vol. 2, pp. 627–628. It has previously been proposed by the inventor to minimize clock skew by using low-impedance lines with matched terminations and current mode signaling to give well-defined delays along clock distribution lines (U.S. patent application Ser. No. 09/385,383 and U.S. patent application Ser. No. 09/386,505) and using lines with zero or no apparent delay of the clock signal (U.S. patent application Ser. No. 09/385,379).
However, there remains a need for solving the problems caused by clock skew at multiple locations in integrated circuits, and, in particular, there is a need for reducing clock skew to acceptable levels in high performance microprocessors and other high speed chips in which small clock edge times and low interconnect resistances cause inductance effects. There is also a need for a method for distributing clock signals without skew and without consuming large amounts of power or chip space.